********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
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*Jul 21, 2014
*ECN S14-1441, Rev. A
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT SiRA16DP D G S 
M1 3 GX S S NMOS W= 3825000u L= 0.30u 
M2 S GX S D PMOS W= 3825000u L= 0.14u 
R1 D 3 4.2884e-03 3.157e-03 8.733e-06 
CGS GX S 1.379e-09 
CGD GX D 1.008e-13 
RG G GY 1 
RTCV 100 S 1e6 -2.666e-04 3.279e-06 
ETCV GX GY 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD S D DBD 3825000u 
**************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 5e-8 
+ RS = 0 KP = 8.399e-06 NSUB = 8.930e+16 
+ KAPPA = 1.0591e-01 NFS = 2.000e+11
+ LD = 0 IS = 0 TPG = 1 CAPOP = 12 ) 
*************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 5e-8 
+NSUB = 3.378e+16 IS = 0 TPG = -1 CAPOP = 12 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 4.364e-08 TREF = 25 BV = 31 
+RS = 3.062e-02 N = 1.035e+00 IS = 2.009e-12 
+EG = 1.177e+00 XTI = -1.0479e+00 TRS = 1.000e-05
+CJO = 4.967e-10 VJ = 5.970e+00 M = 1.000e+00 ) 
.ENDS 
